1. Field of the Invention
The present invention relates to semiconductor memory devices and a method of manufacturing the same, and more particularly, to a semiconductor memory device which can improve reliability by forming a conductive layer so as to surround a memory cell array region on a boundary region between the memory cell array region and a peripheral circuit region, and a method of manufacturing the same.
2. Description of the Background Art
Conventionally, various studies on a semiconductor memory device have been made. According to characteristics and functions, several kinds of semiconductor memory devices such as ROM, SRAM, DRAM and the like have been developed. Description will be given hereinafter by taking a stacked gate type EPROM (erasable and programmable read only memory) as an example of the semiconductor memory devices.
FIG. 25 is a partial cross sectional view showing a schematic configuration of a conventional stacked gate type EPROM. Referring to FIG. 25, the conventional EPROM includes a memory cell array region in which a memory transistor is formed, a peripheral circuit region in which peripheral circuits carrying out operation control of the memory transistor are formed, and a boundary region formed in a boundary portion between the memory cell array region and the peripheral circuit region. An isolation oxide film or the like is ordinarily formed in the boundary region.
As shown in FIG. 25, field oxide films 52, 52a are spaced on the main surface of a semiconductor substrate 51. A floating gate electrode 56 is formed on the memory cell array region on the main surface of semiconductor substrate 51 with a gate insulating film 53 interposed therebetween. A control gate electrode 58 is formed on floating gate electrode 56 with an interlayer insulating film 57 interposed therebetween. The memory transistor is configured of control gate electrode 58, interlayer insulating film 57 and floating gate electrode 56.
On the other hand, in the peripheral circuit region on the main surface of semiconductor substrate 51, a gate electrode 54 is formed with gate insulating film 53 interposed therebetween. A part of the peripheral circuits is configured of a transistor including gate electrode 54. Field oxide film 52a is formed in the boundary region on the main surface of semiconductor substrate 51. An interlayer insulating film 59 is formed so as to cover the above-described memory transistor, field oxide films 52, 52a and gate electrode 54.
A contact hole 61 is formed at a predetermined position in interlayer insulating film 59. An interconnection layer 60 of aluminum (Al) or the like is selectively formed on interlayer insulating film 59 including the inner surface of contact hole 61.
A method of manufacturing the conventional EPROM having the above-described configuration will now be described with reference to FIGS. 26 to 30. FIGS. 26 to 30 are partial cross sectional views showing the first to the fifth steps of the manufacturing process of the conventional EPROM.
Referring to FIG. 26, field oxide films 52, 52a are formed on the main surface of semiconductor substrate 51 by selectively applying a thermal oxidation process. Gate insulating film 53 is formed on the entire main surface of semiconductor substrate 51. Then, a first conductive layer 56a of poly-crystalline silicon or the like having the film thickness of approximately 1000 .ANG. to 1500 .ANG. is deposited by using a CVD (Chemical Vapor Deposition) method or the like.
First conductive layer 56a is patterned to be left in the memory cell array region. Then, an insulating layer 57a having the film thickness of approximately 300 .ANG. of a silicon field film or in a combined structure of a silicon oxide film and a silicon nitride film is formed on first conductive layer 56a. A second conductive layer 55a of poly-crystalline silicon or the like having the film thickness of approximately 2000 .ANG. to 3000 .ANG. is deposited on insulating layer 57a, on field oxide film 52a positioned in the boundary region, and on the peripheral circuit region by using the CVD method or the like.
A first mask layer 66 of resist or the like is applied to second conductive layer 55a. As shown in FIG. 27, first mask layer 66 is patterned to have a portion covering the memory cell array region and having an end portion 66a on field oxide film 52a in the boundary region, and portions selectively formed in the peripheral circuit region. Referring to FIG. 28, by applying an etching process with first mask layer 66 used as a mask, gate electrode 54 is formed in the peripheral circuit region. Then, first mask layer 66 is removed.
A second mask layer 67 of resist or the like is applied to the entire main surface of semiconductor substrate 51. Then, second mask layer 67 is patterned. As a result, as shown in FIG. 29, second mask layer 67 is formed having a portion covering the peripheral circuit region and having an end portion 67a on field oxide film 52 in the boundary region, and portions selectively formed on second conductive layer 55a in the memory cell array region.
Second mask layer 67 is patterned so that end portion 67a of second mask layer 67 positioned on field oxide film 52a formed in the boundary region is not positioned over second conductive layer 55a extending over field oxide film 52a formed in the boundary region.
Description will be given to the reason why end portion 67a of second mask layer 67 is formed not to be positioned over second conductive layer 55a on field oxide film 52a.
Even if second conductive layer 55a is left in the boundary region, second conductive layer 55a does not serve as an interconnection layer. Therefore, it was not considered that it is preferred that second conductive layer 55a not serving as the interconnection layer is left in the boundary region. Therefore, patterning was carried out so that end portion 66a of first mask layer 66 and end portion 67a of second mask layer 67 are positioned with a predetermined space so as not to overlap with each other on field oxide film 52a in the boundary region.
Referring to FIG. 30, by applying an etching process with second mask layer 67 used as a mask, floating gate electrode 56, interlayer insulating film 57, and control gate electrode 58 are formed in the memory cell array region. Then, referring to FIG. 25, interlayer insulating film 59 is formed on the entire main surface of semiconductor substrate 51 by using the CVD method or the like. Contact hole 61 is formed at a predetermined position of interlayer insulating film 59. Interconnection layer 60 of aluminum (Al) or the like is selectively formed on interlayer insulating film 59 including the inner surface of contact hole 61 by using a sputtering method or the like. The conventional EPROM shown in FIG. 18 is formed in the above-described steps.
However, a semiconductor memory device represented by the conventional EPROM had the following problems, which will be described with reference to FIGS. 30 and 31. FIG. 31 is a partial cross sectional view showing in the same figure first mask layer 66 and second mask layer 67 used in the manufacturing process of the conventional EPROM. Therefore, a portion 69a on the memory cell array region in which second mask layer 167 is positioned over first mask layer 66, and a portion 69b on the peripheral circuit region in which first mask layer 66 is positioned over second mask layer 67 are shown in FIG. 31.
As shown in FIG. 31, end portion 66a of first mask layer 66 and end portion 67a of second mask layer 67 on field oxide film 52a in the boundary region are formed so as not to overlap with each other. It was for preventing a remainder of second conductive layer 55a from being formed on field oxide film 52a in the boundary region, as described above.
An etching process is sequentially applied with first and second mask layers 66, 67 used as masks. As show in FIG. 30, when forming floating gate electrode 56, interlayer insulating film 57, and control gate electrode 58, a concave portion 68 is formed on field oxide film 52a in the boundary region.
The depth of concave portion 68 depends on the etching conditions. However, when the film thickness of first conductive layer 56a is approximately 1000 .ANG. to 1500 .ANG., the film thickness of insulting layer 57a is approximately 300 .ANG., the film thickness of second conductive layer 55a is approximately 2000 .ANG. to 3000 .ANG., and the film thickness of field oxide films 52, 52a is approximately 4000 .ANG. to 5000 .ANG., as described above, concave portion 68 of depth of more than approximately 1000 .ANG. to 2000 .ANG. may be formed.
By formation of concave portion 68, it is considered that the upper interconnection layer formed so as to extend over field oxide film 52 may be disconnected. Due to formation of concave portion 68, occurrence of leakage current is also possible. Since the depth of concave portion 68 may be larger depending on the etching conditions, the above-described problems become more serious.
On the other hand, it is considered that positions of end portions 66a, 67a of first and second mask layers 66, 67 are adjusted so that concave portion 68 causing the above-described problems will not be formed. However, in order to pattern first mask layer 66 and second mask layer 67 so that concave portion 68 will not be formed, it is necessary to match positions of end portion 66a of first mask layer 66 and end portion 67a of second mask layer 67. In order to achieve this, patterning of high accuracy is required, implementation of which is considered to be very difficult.
By patterning first and second mask layers 66, 67 as described above, there is a high possibility that second conductive layer 55a of a critical dimension is left on field oxide film 52a. When second conductive layer 55a of a critical dimension is left on field oxide film 52a, separation of second conductive layer 55a therefrom may damage the semiconductor, possibly causing reliability of the semiconductor device to decrease. Therefore, formation of concave portion 68 has conventionally been inevitable.
Other than the above-described problems, a semiconductor memory device such as the conventional EPROM also has the following problems. It is considered that a power supply potential applied to a semiconductor chip will be of a small value in the future. Accordingly, an internal electric field in the memory cell array region, for example, will be weak. As a result, there is a possibility that an influence of an external noise on the inside of the memory cell array region cannot be ignored.
However, in the semiconductor memory device such as the conventional EPROM, a unit for protecting the memory cell array region was not provided. Therefore, in the future, the situation where the influence of the external noise cannot be ignored is also possible.